import chisel3._
//// Chisel Code: Declare a new module definition
//class Passthrough extends Module {
//  val io = IO(new Bundle {
//    val in = Input(UInt(4.W))
//    val out = Output(UInt(4.W))
//  })
//  io.out := io.in
//}
//object Passthrough extends App {
//  println(getVerilogString(new Passthrough))
//}
// Chisel Code, but pass in a parameter to set widths of ports
class PassthroughGenerator(width: Int) extends Module { 
  val io = IO(new Bundle {
    val in = Input(UInt(width.W))
    val out = Output(UInt(width.W))
  })
  io.out := io.in
  printf("Print during simulation: Input is %d\n", io.in)
  // chisel printf has its own string interpolator too
  printf(p"Print during simulation: IO is $io\n")

  println(s"Print during generation: Input is ${io.in}")
}

// Let's now generate modules with different widths
object Passthrough extends App {
  //println(emitFirrtl(new PassthroughGenerator(10)))
  println(getVerilogString(new PassthroughGenerator(10)))
  //println(emitFirrtl(new PassthroughGenerator(20)))  
  println(getVerilogString(new PassthroughGenerator(20)))
}
